4.1 Solid-state electronic devices subjected to stresses from excessive current pulses sometimes fail because a portion of the metallization fuses or vaporizes (suffers burnout). Burnout susceptibility can vary significantly from component to component on a given wafer, regardless of design. This practice provides a procedure for establishing the limits of pulse current overstress within which the metallization of a given device should survive.

4.2 This practice can be used as a destructive test in a lot-sampling program to determine the boundaries of the safe operating region having desired survival probabilities and statistical confidence levels when appropriate sample quantities and statistical analyses are used.

1.1 This practice covers procedures for determining operating regions that are safe from metallization burnout induced by current pulses of less than 1-s duration.

1.2 This practice is based on the application of unipolar rectangular current test pulses. An extrapolation technique is specified for mapping safe operating regions in the pulse-amplitude versus pulse-duration plane. A procedure is provided in Appendix X2 to relate safe operating regions established from rectangular pulse data to safe operating regions for arbitrary pulse shapes.

1.3 This practice is not intended to apply to metallization damage mechanisms other than fusing or vaporization induced by current pulses and, in particular, is not intended to apply to long-term mechanisms, such as metal migration.

1.4 This practice is not intended to determine the nature of any defect causing failure.

1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.