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IEC 62050:2005 ed1.0
VHDL Register Transfer Level (RTL) synthesis
121 стр.
Отменен
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540.54 CHF (включая НДС 20%)
Разработчик:
Зарубежные/IEC
ICS:
25.040.01 Industrial automation systems in general / Промышленные автоматизированные системы в целом35.240.50 IT applications in industry. Including design automation / Применение информационных технологий в промышленности. Включая автоматизацию проектирования
Описание
Specifies a standard for use of very high-speed integrated circuit hardware description language (VHDL) to model synthesizable register-transfer level digital logic. A standard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors.