Defines a mechanism for the test of core designs within a system on chip (SoC).This mechanism constitutes a hardware architecture and leverages the core test language (CTL)to faciliate communication between core designers and core integrators.
ICS
31.200 Integrated. Including electronic chips, logical and analogue microstructures / Интегральные схемы. Микроэлектроника. Включая электронные микросхемы, логические и аналоговые микроструктуры